The tri-gate transistor isn’t entirely a new announcement, as the company has been talking about the technology at various events since September of 2002. Presenting at the 2006 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, intel followed up with more details and first test results, which indicated that the tri-gate transistor, often also referred to as “3D transistor” may in fact be a technology that will make it into production one day.
With the amount of transistors doubling every 18 – 24 months company is inclined more and more tio reduce the transistor size which essentially lies on reducing the sorce , drain, gates size. Reducing the gate size created several challenges such as increasing current leakage in “off” states of a transistor – causing the overall power consumption of a semiconductor device to climb. Power consumption has been a major consideration in Chip design technology.
First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50x reduction in “off”-current when compared to regular planar transistors.
Hmm lall this is pretty interesting. Lets wait and see how far companies reduce the size and power consumption in future.
Here are few pics of actual transistor.
1)Abstract view of today’s planar transistor technology in Intel semiconductors. Each transistor has only one gate.
2)Photograph of an actual transistor. In the current 65 nm processor generation, the gate is about 35 nm wide, the gate oxide insulator, located between the gate electrode and the silicon substrate is just 1.2 nm thin. With each new generation, the insulator layer gets thinner and the control of current leakage gets more difficult.
3)One solution to control leakage and enhance the flow of main current: Gates on three sides of the silicon substrate, not just on one.
4)Side-view of an actual tri-gate transistor. The main current “fin” is covered by gate insulators on three out of four sides. These tri-gate prototypes also use a “high-K” material to insulate the gate – instead of today’s silicon dioxide gate dielectric. Intel will switch to this new “secret” material with the 45 nm processor generation.
5)Multiple tri-gate transistors: The gates wrap-around the current fin. Intel claims that 65 nm tri-gate transistors offer a 45% increase in speed or 50x reduction in “off”-current when compared to regular planar transistors. Tri-gate transistors could see mass production with 32 nm processors in 2009.
6) Tri-gate isn’t the best solution. Scientists are looking for ways to build the perfect transistor, pictures in a simplified model here. The insulator (red) of the gate (green) completely wraps around the electron flow (blue) and provides a maximum of transistor efficiency. At least today, manufacturing technologies cannot create such a current “tunnel.”
Well this information specifically amused me because i like the real pictures of the transistors and the new conceopt of 3D-Trans…. 🙂
Thanks to htp://.tgdaily.com